1. Field of the Invention
The present invention relates to a bus controlling method and equipment. More particularly, in a case where a plurality of devices are accessed through a common bus, the present invention relates to a method for controlling a bus cycle for each device and to equipment using the method.
2. Description of the Related Arts
A variety of data processing equipment such as PCs usually have microprocessors which centrally control the entire equipment. A microprocessor is connected to a variety of memories and I/O devices through buses such as a local bus and a system bus. In recent microprocessors, a cache memory and a circuit regarding a communication function are often installed. However, for memories other than a cache memory or I/O devices, microprocessors access them by performing an ordinary bus cycle.
FIG. 4 is a timing chart of a bus cycle described on page 125 of xe2x80x9cHitachi single chip RISC microcomputers SH7032, SH7034, HD6417032, HD6477034, and HD6437034 hardware manuals (third edition)xe2x80x9d . In this figure, CK denotes an operation clock of the microcomputer, and A21xcx9c0 are addresses for addressing external devices. *CSn represents a chip select asserted when an nth space (hereafter simply called address space n) of address spaces partitioned into a plurality of spaces is accessed, and *RD is a read command which is active on a low signal level. AD15xcx9c0 unit data. Hereafter, a signal prefixed with * unit the signal which is active on a low signal level.
In FIG. 4, one period of the clock CK is equivalent to each state T1, or T2. If the configuration is as simple as possible, each device is assigned to each address space n on a one to one basis, and the address space n becomes an exclusive space for the device. Therefore, each device has a connection with one chip select *CS.
One of the characteristics of the microcomputer in FIG. 4 is that it can change an assertion timing of a read command *RD. As shown in the figure, if RDDTY=0, the assertion timing is set to be slightly later, while it is set to be slightly earlier if RDDTY=1. The signal RDDTY can respectively be set for each address space n. According to the manual description, an access time to an external device can be set long by setting RDDTY=1.
For the microcomputer described above, the assertion timing of the read command can respectively be set for each device to be accessed. This is a technique which takes an access time to a device into consideration.
On the other hand, when timings regarding a bus cycle are designed, an output disable time of a device should be considered in some cases. An output disable time is the time from negation timing of a read command to the device to a timing when a data buffer of the device actually becomes OFF so that an output from that device completely floats. If this output disable time is long and the next bus cycle is a write cycle, for example, a conflict occurs on the bus between the output from the device and a write data. This leads to an increased power consumption and a lower long term reliability of the device. Even when the next bus cycle is a read cycle, outputs from two devices may conflict. The possibility of data conflict will be lowered if a read command is negated earlier. However, for an ordinary IC, the lowermost output disable time is set to fall within 0xcx9cseveral ns in the standard. Therefore, it is possible for read data to float before the data is taken in. It is generally risky to design a read command to be negated early. Therefore, design with consideration of the output disable time can be very troublesome in some cases.
In the case of the microcomputer shown in FIG. 4, an inactive time of a read command can be extended by making RDDTY =0. For this reason, if the read cycle is repeated, output timing of read data from a device shifts later, and the possibility of data conflict between the data and read data from a device previously selected is lowered. However, if a write cycle comes after a read cycle, a data conflict can not be avoided.
The present invention is created from consideration of the problem described above. The object of the present invention is to provide a bus controlling method and equipment for a plurality of devices with different output disable times, which prevents data conflicts from occurring while avoiding performance degradation. Another object of the present invention is to automatically perform such control using pre-set parameters or the like. Still another object of the present invention is to provide a bus controlling method and equipment which enables easier design of external circuits.
1. Regarding a Bus Controlling Method
A principle to solve the problem described above is, for controlling a bus cycle BCi, to refer to the immediately preceding bus cycle BCixe2x88x921. In other words, based on a characteristic of a device accessed in BCixe2x88x921, for example, an output disable time thereof, activation of BCi is delayed if necessary after the end of BCixe2x88x921. Here, xe2x80x9cdevicesxe2x80x9d unit general targets to be accessed.
The problem of the prior art can be solved with the present invention, since a bus cycle control is performed in response to the immediately preceding bus cycle. One method to delay a bus cycle activation is to insert an idle state.
In one aspect of the present invention, a characteristic of a device to be accessed in BCixe2x88x921 is specified by referring to:
a. an address being output when each device is allocated in an exclusive address space, and
b. the number of wait cycles in the current bus cycle or the like.
According to the present invention, activation of BCi is delayed only when it is necessary. Therefore, a data conflict can be avoided without leading to unnecessary degradation of processing performance. When the output disable time is considered as a characteristic of a device, the device with a long output disable time is often a low speed device. Therefore, when the present invention is implemented, a low speed device may be specified. This method has high practicality, although it is simple.
In another aspect of the present invention, if the device having output data in BCixe2x88x921 is also the device to output data in BCi, BCi is activated without delay. This is because no conflict occurs when data are output from the same single device. Device here is meant to include a microprocessor and the like. Therefore, according to this aspect, when a microprocessor carries out a writing operation continuously to a device, BCi will not be delayed unnecessarily.
2. Regarding Bus Controlling Equipment
The present invention comprises setting unit for setting a parameter related to an output disable time of a device to be accessed, and bus controlling unit for inserting an idle state after a current bus cycle in response to an output disable time of a device being accessed in the current bus cycle, based on the parameter set by the setting unit. The xe2x80x9cparameter related to the output disable timexe2x80x9d is meant to include all parameters to judge or estimate not only the output disable time itself but also whether the output disable time is long or short.
With this configuration, the effect same as 1 described above can be realized for equipment. A work load for designing a circuit outside the equipment is also reduced, since this equipment considers output disable times by itself.
One aspect of the present invention comprises judging unit for judging whether or not a device to output data in a current bus cycle is also a device to output data in the following bus cycle, and prohibition unit for prohibiting insertion of the idle state after the current bus cycle if the devices are judged to be the same. As described in 1 above, no data conflict occurs when one and the same device continuously outputs data. Unnecessary delays will be avoided by taking such cases into consideration.